Graduate Verification Engineer

Key responsibilities:

• Verification planning, maintenance, feature extraction, verification test case and checker development
• Collaborate effectively with the US, India and UK based Design and Verification teams.
• Assist in integrating design verification processes to achieve first-pass silicon success, performance goals, and schedule compliance.
• Perform any additional tasks as assigned by the Lead/manager.

Qualifications

• 0–1 years of experience in AMS (Analog Mixed-Signal) verification, mixed-signal IC design, or a related area.
• Proficient in at least one of the following: Verilog, SystemVerilog, or Verilog-AMS.
• Fundamental understanding of analog circuits, digital design flow, and mixed-signal top-level integration.
• Basic knowledge of PMICs, DC-DC converters, and power management concepts is a plus.
• Familiarity with simulation debugging, including waveform analysis and identifying issues in schematics, behavioral models, or RTL.
• Comfortable working in a Unix/Linux environment; exposure to shell scripting and basic Python is desirable.
• Ability to use AI-based tools and technologies to enhance engineering efficiency, automate routine tasks, and support debugging and analysis.

Non-Technical Skills

• Concise and proactive communication skills within a multi-side and multi-cultural environment.
• Results-oriented and able to deliver on-time under tight schedule pressure.
• Provide frequent reports on progress status and roadblocks, ensuring transparent communication with stakeholders.